1. Technical Field
Various exemplary embodiments relate to a semiconductor memory device and a memory system including the same.
2. Related Art
Semiconductor memory devices are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices may be divided into dynamic random access memory (DRAM) devices and static RAM (SRAM) devices. Although the volatile semiconductor memory device reads and writes data at a high speed, the volatile semiconductor memory device loses stored data when external power supply is interrupted. The nonvolatile semiconductor memory devices may be divided into mask read-only memory (MROM) devices, programmable ROM (PROM) devices, erasable programmable ROM (EPROM) devices, and electrically erasable programmable ROM (EEPROM) devices. A nonvolatile semiconductor memory device retains stored data even if the external power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store data that should be retained irrespective of whether or not power is supplied.
A typical semiconductor memory device has a redundancy structure in which, when some of memory cells in the semiconductor memory device are defective, the defective cells are replaced by redundant cells to improve the performance of the entire chip. With increases in the integration density and capacity of semiconductor memory devices, the above-described redundancy structure has been necessitated. The redundancy structure of the semiconductor memory devices may be divided into a row redundancy structure and a column redundancy structure. In the row redundancy structure, when an element of a defective cell has a row directional defect, a row address is decoded using fuse cutting or a content addressable memory (CAM) cell to disable a word line of the defective cell and enable a word line of a redundant cell, so that the redundant cell may be used instead of the defective cell. When an element of a defective cell has a column directional defect, a column address is decoded using fuse cutting or a CAM cell to disable a column selection line of the defective cell and enable a column selection line of a redundant cell, so that the column directional defect may be repaired.
FIG. 1 is a block diagram illustrating a typical semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device 10 may include a plurality of memory banks, i.e., first and second memory banks BANK0 and BANK1. Each of the first and second memory banks BANK0 and BANK1 may include a low-byte main memory unit 11, a high-byte main memory unit 12, a low redundancy memory unit 13, and a high redundancy memory unit 14 corresponding respectively to the low-byte main memory unit 11 and the high-byte main memory unit 12.
Since the semiconductor memory device 10 includes 32 global data lines and data are communicated through 8 I/O data lines IO during I/O operations, each of the first and second memory banks BANK0 and BANK1 includes the low-byte main memory unit 11 and the high-byte main memory unit 12 to be divided into four units. When defective columns occur, the low redundancy memory unit 13 and the high redundancy memory unit 14 may be required to repair the defective columns in the low-byte main memory unit 11 and the high-byte main memory unit 12. Since the low-byte main memory unit 11 and the high-byte main memory unit 12 use different I/O data lines IO/IOb<7:0> and IO/IOb<15:8>, many defective cells may occur in any one of the low-byte main memory unit 11 and the high-byte main memory unit 12. Thus, one of the low redundancy memory unit 13 and the high redundancy memory unit 14 is used excessively and may not program data any longer. Even if the other of the low redundancy memory unit 13 and the high redundancy memory unit 14 may additionally program data, the redundancy memory unit is not connected to the respective data lines, and may degrade redundancy efficiency.